The disclosure relates to frequency switching techniques for a system clock signal, and more particularly, to system clock switching apparatuses and related methods that avoid drift of enable signals corresponding to the system clock signal while switching the frequency of the system clock signal.
In a synchronous circuit, each individual module or component synchronously operates according to a system clock signal. The synchronous circuit may change or switch the frequency of the system clock signal to meet different operational requirements. For example, power consumption can be reduced by lowering the frequency of the system clock signal. In the related art, a phase-locked loop (PLL) or a digital frequency divider is typically employed to change or switch the frequency of the system clock signal.
In addition to the system clock signal, the synchronous circuit further utilizes one or more enable signals with fixed frequency to maintain the system functionalities. For example, a GSM communication system requires an enable signal QBIT_EN for determining the timing of signal transmission and reception. If the enable signal drifts, the communication quality and performance of the GSM system is seriously deteriorated.
As mentioned previously, the PLL is widely employed to switch frequencies of system clock signals in the related art. As is well known in the art, when the PLL switches the frequency of an output clock signal, a settling time is required for the frequency of the output clock signal to reach a stable status again. During the settling time, the enable signal often drifts since the frequency of the output clock signal generated from the PLL is not stable.
Please refer to FIG. 1, which shows a block diagram of a conventional system clock generating device 100. The system clock generating device 100 utilizes a PLL 110 to generate a clock signal PCLK as a system clock signal SCLK of a system circuit 130. As mentioned above, the PLL 100 requires a settling time for the frequency of the clock signal PCLK to reach a stable status again while changing the frequency of the clock signal PCLK. To avoid the operations of the system circuit 130 from being negatively affected by the unstable frequency of the clock signal PCLK within the settling time, the multiplexer 120 bypasses the clock signal PCLK from the PLL 110 and instead selects an external clock signal XCLK with a fixed frequency to be the system clock signal SCLK. When the PLL 110 reaches a new stable status, the multiplexer 120 switches the system clock signal SCLK from the external clock signal XCLK to the clock signal PCLK generated by the PLL 110.
Hereinafter, a conventional method of switching the system clock signal SCLK is described by employing the operations of switching the frequency of the clock signal PCLK from 52 MHz to 26 MHz made by the PLL 110 as an example.
First, the multiplexer 120 bypasses the clock signal PCLK (52 MHz) from the PLL 110 and switches the system clock signal SCLK to the external clock signal XCLK. Next, the PLL 110 adjusts the frequency of the clock signal PCLK to 26 MHz. After the PLL 110 reaches a stable status, the multiplexer 120 switches the system clock signal SCLK from the external clock signal XCLK to the clock signal PCLK (26 MHz) from the PLL 110.
However, the multiplexer 120 switches the system clock signal SCLK from the clock signal PCLK to the external clock signal XCLK or from the external clock signal XCLK to the clock signal PCLK is an asynchronous clock switching operation. Thus, the clock signal PCLK from the PLL 110 and the external clock signal XCLK may be different in phase or frequency during the switching operation. As a result, it is difficult to maintain the period of the enable signal constantly while switching the frequency of the system clock signal SCLK and thereby causing the enable signal to drift.
As mentioned above, the digital frequency divider can be employed to generate the system clock signal of different frequency in the related art. However, employment of the digital frequency divider may also cause the enable signal to drift. In general, the enable signal is generated from a counter. Please refer to the example illustrated in FIG. 2, which depicts a block diagram of a conventional system clock generating device 200 while applying a digital frequency divider to change a frequency of the system clock signal. A digital frequency divider 210 of the system clock generating device 200 divides a reference clock signal RCLK which has a fixed frequency for generating a system clock signal SCLK. A counter 220 then generates an enable signal according to the system clock signal SCLK. Take the enable signal QBIT_EN that has a frequency of 13/12 MHz for example. When the frequency of the system clock signal SCLK generated from the digital frequency divider 210 is 52 MHz, the counter 220 generates an enable signal QBIT_EN every forty-eight system clock periods. When the frequency of the system clock signal SCLK is 13 MHz, the counter 220 generates an enable signal QBIT_EN every twelve system clock periods. However, the digital frequency divider 210 may switch the frequency of the system clock signal SCLK at any time, and frequency switch therefore may change the period of the enable signal QBIT_EN generated by the counter 220.
Please refer to FIG. 3 and FIG. 4. FIG. 3 shows a timing diagram of the enable signal QBIT_EN with a lengthened period. As shown in FIG. 3, the system clock signal SCLK is lengthened when the digital frequency divider 210 switches the frequency of the system clock signal SCLK from 52 MHz to 13 MHz. As detailed in the aforementioned descriptions, when the frequency of the system clock signal SCLK is 52 MHz, the counter 220 generates an enable signal QBIT_EN every forty-eight system clock periods, i.e., once the counter 220 counts from forty-seven to zero (the count value QBIT_CNT from forty-seven to zero), an enable signal QBIT_EN is generated. If the digital frequency divider 210 does not switch the frequency of the system clock signal SCLK, the count value sequence of the counter 220 should be equal to QBIT_CNT(expected) and the counter 220 should generate the enable signal when the count value QBIT_CNT(expected) is zero, such as the QBIT_EN(expected) shown in FIG. 3. However, because the frequency of the system clock signal SCLK is switched from 52 MHz to 13 MHz, the system clock period is lengthened and the counting period of the counter 220 is extended. Therefore, the actual count value sequence from the counter 220 is QBIT_CNT. As a result, the time at which the enable signal QBIT_EN occurs is delayed and the period of the enable signal is lengthened, thereby causing the enable signal to drift.
As shown in FIG. 4, the system clock signal SCLK is shortened when the frequency of the system clock signal SCLK is switched from 13 MHz to 52 MHz. As detailed in the aforementioned descriptions, when the frequency of the system clock signal SCLK is 13 MHz, the counter 220 generates an enable signal QBIT_EN every twelve system clock periods, i.e., once the counter 220 counts from eleven to zero (the count value QBIT_CNT from eleven to zero), an enable signal QBIT_EN is generated. If the digital frequency divider 210 does not switch the frequency of the system clock signal SCLK, the counter 220 should generate the enable signal when the count value QBIT_CNT(expected) is zero, such as the QBIT_EN(expected) shown in FIG. 4. However, because the frequency of the system clock signal SCLK is switched from 13 MHz to 52 MHz, the system clock period is shortened and the counting period of the counter 220 is thereby shortened.
As a result, the time at which the enable signal QBIT_EN occurs is advanced and the period of the enable signal is shortened, thereby causing the enable signal to drift.